[embeded] Port u-boot to mini2440 (2)
Step one -> Port NAND flash driver:
1.Edit /deivers/mtd/nand/s3c2410_nand.c
diff -uNr u-boot-2009.08_0319_ok/drivers/mtd/nand/s3c2410_nand.c u-boot-2009.08_nand/drivers/mtd/nand/s3c2410_nand.c
--- u-boot-2009.08_0319_ok/drivers/mtd/nand/s3c2410_nand.c 2017-03-19 15:24:54.000000000 +0800
+++ u-boot-2009.08_nand/drivers/mtd/nand/s3c2410_nand.c 2017-04-25 14:17:10.341918688 +0800
@@ -34,6 +34,8 @@
#define __REGi(x) (*(volatile unsigned int *)(x))
#define NF_BASE 0x4e000000
+
+#if 0
#define NFCONF __REGi(NF_BASE + 0x0)
#define NFCMD __REGb(NF_BASE + 0x4)
#define NFADDR __REGb(NF_BASE + 0x8)
@@ -42,7 +44,9 @@
#define NFECC0 __REGb(NF_BASE + 0x14)
#define NFECC1 __REGb(NF_BASE + 0x15)
#define NFECC2 __REGb(NF_BASE + 0x16)
+#endif
+#if defined(CONFIG_S3C2410)
#define S3C2410_NFCONF_EN (1<<15)
#define S3C2410_NFCONF_512BYTE (1<<14)
#define S3C2410_NFCONF_4STEP (1<<13)
@@ -54,44 +58,64 @@
#define S3C2410_ADDR_NALE 4
#define S3C2410_ADDR_NCLE 8
+#endif
+
+#if defined(CONFIG_S3C2440)
+#define S3C2410_NFCONT_EN (1<<0)
+#define S3C2410_NFCONT_INITECC (1<<4)
+#define S3C2410_NFCONT_nFCE (1<<1)
+#define S3C2410_NFCONT_MAINECCLOCK (1<<5)
+#define S3C2410_NFCONF_TACLS(x) ((x)<<12)
+#define S3C2410_NFCONF_TWRPH0(x) ((x)<<8)
+#define S3C2410_NFCONF_TWRPH1(x) ((x)<<4)
+
+#define S3C2410_ADDR_NALE 0x08
+#define S3C2410_ADDR_NCLE 0x0c
+#endif
+
+ulong IO_ADDR_W = NF_BASE;
static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *chip = mtd->priv;
+ //struct nand_chip *chip = mtd->priv;
+ S3C2410_NAND *nand = S3C2410_GetBase_NAND();
DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = NF_BASE;
+ IO_ADDR_W = (ulong)nand;
if (!(ctrl & NAND_CLE))
IO_ADDR_W |= S3C2410_ADDR_NCLE;
if (!(ctrl & NAND_ALE))
IO_ADDR_W |= S3C2410_ADDR_NALE;
- chip->IO_ADDR_W = (void *)IO_ADDR_W;
+ //chip->IO_ADDR_W = (void *)IO_ADDR_W;
if (ctrl & NAND_NCE)
- NFCONF &= ~S3C2410_NFCONF_nFCE;
+ nand->NFCONT &= ~S3C2410_NFCONT_nFCE;
else
- NFCONF |= S3C2410_NFCONF_nFCE;
+ nand->NFCONT |= S3C2410_NFCONT_nFCE;
}
if (cmd != NAND_CMD_NONE)
- writeb(cmd, chip->IO_ADDR_W);
+ writeb(cmd, (void *)IO_ADDR_W);
}
static int s3c2410_dev_ready(struct mtd_info *mtd)
{
+ S3C2410_NAND *nand = S3C2410_GetBase_NAND();
DEBUGN("dev_ready\n");
- return (NFSTAT & 0x01);
+ return (nand->NFSTAT & 0x01);
}
#ifdef CONFIG_S3C2410_NAND_HWECC
void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
+ S3C2410_NAND *nand = S3C2410_GetBase_NAND();
+
DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
- NFCONF |= S3C2410_NFCONF_INITECC;
+ nand->NFCONT |= S3C2410_NFCONT_INITECC;
}
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
@@ -124,23 +148,27 @@
u_int32_t cfg;
u_int8_t tacls, twrph0, twrph1;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ S3C2410_NAND *nand_reg = S3C2410_GetBase_NAND();
DEBUGN("board_nand_init()\n");
clk_power->CLKCON |= (1 << 4);
/* initialize hardware */
- twrph0 = 3; twrph1 = 0; tacls = 0;
+ twrph0 = 4; twrph1 = 2; tacls = 0;
- cfg = S3C2410_NFCONF_EN;
+ cfg = 0;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
- NFCONF = cfg;
+ nand_reg->NFCONF = cfg;
+
+ cfg = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(0<<6)|(0<<5)|(1<<4)|(0<<1)|(1<<0);
+ nand_reg->NFCONT = cfg;
/* initialize nand_chip data structure */
- nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c;
+ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
Step two -> Enable DM9000 driver:
1.Edit /drivers/net/dm9000x.c
diff -uNr u-boot-2009.08_0319_ok/drivers/net/dm9000x.c u-boot-2009.08_nand/drivers/net/dm9000x.c
--- u-boot-2009.08_0319_ok/drivers/net/dm9000x.c 2017-03-19 15:24:55.000000000 +0800
+++ u-boot-2009.08_nand/drivers/net/dm9000x.c 2017-04-24 15:21:49.847997780 +0800
@@ -374,9 +374,10 @@
while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
udelay(1000);
i++;
- if (i == 10000) {
- printf("could not establish link\n");
- return 0;
+ if (i == 1000) {
+ // printf("could not establish link\n");
+ // return 0;
+ break;
}
}
2.Edit /net/nfs.c
diff -uNr u-boot-2009.08_0319_ok/net/nfs.c u-boot-2009.08_nand/net/nfs.c --- u-boot-2009.08_0319_ok/net/nfs.c 2017-03-19 15:24:54.000000000 +0800 +++ u-boot-2009.08_nand/net/nfs.c 2017-04-24 15:22:38.703995872 +0800 @@ -33,7 +33,7 @@ #define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ #define NFS_RETRY_COUNT 30 -#define NFS_TIMEOUT 2000UL +#define NFS_TIMEOUT (10*2000UL) static int fs_mounted = 0; static unsigned long rpc_id = 0;
3.Solution for issues about timeout:
Read the documents: u-boot: Retry count exceeded;starting again
http://log.anycle.com/skill/254.html
Step three -> Change some config files for mini2440:
1.Edit /include/s3c24x0.h
diff -uNr u-boot-2009.08_0319_ok/include/s3c24x0.h u-boot-2009.08_nand/include/s3c24x0.h
--- u-boot-2009.08_0319_ok/include/s3c24x0.h 2017-03-19 15:24:58.000000000 +0800
+++ u-boot-2009.08_nand/include/s3c24x0.h 2017-04-24 16:00:02.819908239 +0800
@@ -143,6 +143,9 @@
S3C24X0_REG32 CLKCON;
S3C24X0_REG32 CLKSLOW;
S3C24X0_REG32 CLKDIVN;
+#if defined(CONFIG_S3C2440)
+ S3C24X0_REG32 CAMDIVN;
+#endif
} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
@@ -178,6 +181,7 @@
/* NAND FLASH (see S3C2410 manual chapter 6) */
+#if defined(CONFIG_S3C2410)
typedef struct {
S3C24X0_REG32 NFCONF;
S3C24X0_REG32 NFCMD;
@@ -186,7 +190,27 @@
S3C24X0_REG32 NFSTAT;
S3C24X0_REG32 NFECC;
} /*__attribute__((__packed__))*/ S3C2410_NAND;
-
+#endif
+#if defined(CONFIG_S3C2440)
+typedef struct {
+ S3C24X0_REG32 NFCONF;
+ S3C24X0_REG32 NFCONT;
+ S3C24X0_REG32 NFCMD;
+ S3C24X0_REG32 NFADDR;
+ S3C24X0_REG32 NFDATA;
+ S3C24X0_REG32 NFMECCD0;
+ S3C24X0_REG32 NFMECCD1;
+ S3C24X0_REG32 NFSECCD;
+ S3C24X0_REG32 NFSTAT;
+ S3C24X0_REG32 NFESTAT0;
+ S3C24X0_REG32 NFESTAT1;
+ S3C24X0_REG32 NFMECC0;
+ S3C24X0_REG32 NFMECC1;
+ S3C24X0_REG32 NFSECC;
+ S3C24X0_REG32 NFSBLK;
+ S3C24X0_REG32 NFEBLK;
+} /*__attribute__((__packed__))*/ S3C2410_NAND;
+#endif
/* UART (see manual chapter 11) */
typedef struct {
@@ -339,8 +363,17 @@
S3C24X0_REG8 OUT_FIFO_CNT2_REG;
S3C24X0_REG8 res16[3];
#endif /* __BIG_ENDIAN */
+ //S3C24X0_USB_DEV_FIFOS fifo[5];
+ //S3C24X0_USB_DEV_DMAS dma[5];
+
+ S3C24X0_REG32 res17[8];
S3C24X0_USB_DEV_FIFOS fifo[5];
- S3C24X0_USB_DEV_DMAS dma[5];
+ S3C24X0_REG32 res18[8];
+ S3C24X0_USB_DEV_DMAS ep1;
+ S3C24X0_USB_DEV_DMAS ep2;
+ S3C24X0_REG32 res19[8];
+ S3C24X0_USB_DEV_DMAS ep3;
+ S3C24X0_USB_DEV_DMAS ep4;
} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
@@ -523,6 +556,12 @@
S3C24X0_REG32 GSTATUS2;
S3C24X0_REG32 GSTATUS3;
S3C24X0_REG32 GSTATUS4;
+
+ S3C24X0_REG32 res9[3];
+ S3C24X0_REG32 MSLCON;
+ S3C24X0_REG32 GPJCON;
+ S3C24X0_REG32 GPJDAT;
+ S3C24X0_REG32 GPJUP;
#endif
} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
@@ -717,6 +756,7 @@
S3C24X0_REG32 SDIDCNT;
S3C24X0_REG32 SDIDSTA;
S3C24X0_REG32 SDIFSTA;
+#if 0
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res[3];
S3C24X0_REG8 SDIDAT;
@@ -724,7 +764,14 @@
S3C24X0_REG8 SDIDAT;
S3C24X0_REG8 res[3];
#endif
+#endif
+#if defined(CONFIG_S3C2410)
+ S3C24X0_REG32 SDIDAT;
+ S3C24X0_REG32 SDIIMSK;
+#elif defined(CONFIG_S3C2440)
S3C24X0_REG32 SDIIMSK;
+ S3C24X0_REG32 SDIDAT;
+#endif
} /*__attribute__((__packed__))*/ S3C2410_SDI;
2.Edit /board/mini2440/mini2440.c
diff -uNr u-boot-2009.08_0319_ok/board/mini2440/mini2440.c u-boot-2009.08_nand/board/mini2440/mini2440.c
--- u-boot-2009.08_0319_ok/board/mini2440/mini2440.c 2017-03-19 15:24:51.000000000 +0800
+++ u-boot-2009.08_nand/board/mini2440/mini2440.c 2017-04-24 17:27:18.859703769 +0800
@@ -30,6 +30,7 @@
#include <common.h>
#include <s3c2410.h>
+#include <video_fb.h>
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand.h>
@@ -43,10 +44,10 @@
#define M_MDIV 0xC3
#define M_PDIV 0x4
#define M_SDIV 0x1
-#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
-#define M_MDIV 0x5c
-#define M_PDIV 0x4
-#define M_SDIV 0x0
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ /* 405MHz now */
+#define M_MDIV 0x7f
+#define M_PDIV 0x2
+#define M_SDIV 0x1
#endif
#define USB_CLOCK 1
@@ -56,8 +57,8 @@
#define U_M_PDIV 0x3
#define U_M_SDIV 0x1
#elif USB_CLOCK==1
-#define U_M_MDIV 0x48
-#define U_M_PDIV 0x3
+#define U_M_MDIV 0x38
+#define U_M_PDIV 0x2
#define U_M_SDIV 0x2
#endif
@@ -94,12 +95,12 @@
/* set up the I/O ports */
gpio->GPACON = 0x007FFFFF;
- gpio->GPBCON = 0x00044556;
+ gpio->GPBCON = 0x00295551;
gpio->GPBUP = 0x000007FF;
gpio->GPCCON = 0xAAAAAAAA;
- gpio->GPCUP = 0x0000FFFF;
+ gpio->GPCUP = 0xFFFFFFFF;
gpio->GPDCON = 0xAAAAAAAA;
- gpio->GPDUP = 0x0000FFFF;
+ gpio->GPDUP = 0xFFFFFFFF;
gpio->GPECON = 0xAAAAAAAA;
gpio->GPEUP = 0x0000FFFF;
gpio->GPFCON = 0x000055AA;
@@ -122,9 +123,56 @@
icache_enable();
dcache_enable();
+#if defined(CONFIG_MINI2440_LED)
+ gpio->GPBDAT = 0x00000181;
+#endif
return 0;
}
+#define MVAL (0)
+#define MVAL_USED (0)
+#define INVVDEN (1)
+#define BSWP (0)
+#define HWSWP (1)
+
+//TFT 240320
+#define LCD_XSIZE_TFT_240320 (240)
+#define LCD_YSIZE_TFT_240320 (320)
+
+//TFT 240320
+#define HOZVAL_TFT_240320 (LCD_XSIZE_TFT_240320-1)
+#define LINEVAL_TFT_240320 (LCD_YSIZE_TFT_240320-1)
+
+//Timing parameter for NEC3.5"
+#define VBPD_240320 (3)
+#define VFPD_240320 (10)
+#define VSPW_240320 (1)
+
+#define HBPD_240320 (5)
+#define HFPD_240320 (2)
+#define HSPW_240320_NEC (36)
+#define HSPW_240320_TD (23)
+
+#define CLKVAL_TFT_240320 (3)
+
+void board_video_init(GraphicDevice *pGD){
+ S3C24X0_LCD *const lcd = S3C24X0_GetBase_LCD();//s3c24x0_get_base_lcd();
+ S3C2410_NAND *const nand = S3C2410_GetBase_NAND();//s3c2410_get_base_nand();
+
+ lcd->LCDCON1 = 0x00000378;
+ lcd->LCDCON2 = (VBPD_240320<<24)|(LINEVAL_TFT_240320<<14)|(VFPD_240320<<6)|(VSPW_240320);
+ lcd->LCDCON3 = (HBPD_240320<<19)|(HOZVAL_TFT_240320<<8)|(HFPD_240320);
+
+ if((nand->NFCONF)&0x08){
+ lcd->LCDCON4 = (MVAL<<8)|(HSPW_240320_TD);
+ }else{
+ lcd->LCDCON4 = (MVAL<<8)|(HSPW_240320_NEC);
+ }
+
+ lcd->LCDCON5 = 0x00000f09;
+ lcd->LPCSEL = 0x00000000;
+}
+
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
@@ -133,6 +181,7 @@
return 0;
}
+#if 0
#if defined(CONFIG_CMD_NAND)
extern ulong nand_probe(ulong physadr);
@@ -178,3 +227,14 @@
printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
}
#endif
+
+
+#endif
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis){
+ int rc = 0;
+ rc = dm9000_initialize(bis);
+ return rc;
+}
+#endif
+
3.Edit a very important config file: /include/configs/mini2440.h
diff -uNr u-boot-2009.08_0319_ok/include/configs/mini2440.h u-boot-2009.08_nand/include/configs/mini2440.h --- u-boot-2009.08_0319_ok/include/configs/mini2440.h 2017-03-19 15:24:58.000000000 +0800 +++ u-boot-2009.08_nand/include/configs/mini2440.h 2017-04-25 14:32:11.961911857 +0800 @@ -46,6 +46,8 @@ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2410 SoC */ #define CONFIG_MINI2440 1 /* on a friendly-arm SBC-2410X Board */ +#define CONFIG_MINI2440_LED 1 +#define CONFIG_S3C2410_NAND_SKIP_BAD 1 /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ @@ -63,9 +65,20 @@ /* * Hardware drivers */ +#if 0 #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ #define CS8900_BASE 0x19000300 #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#endif +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x20000300 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_DM9000_NO_SROM 1 +#undef CONFIG_DM9000_DEBUG /* * select serial console configuration @@ -105,17 +118,21 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +//#define CONFIG_CMD_USB #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \ - "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \ - "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" +#define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock3 init=/linuxrc console=ttySAC0" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.0.69 -#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.52 +#define CONFIG_OVERWRITE_ETHADDR_ONCE /*#define CONFIG_BOOTFILE "elinos-lart" */ -#define CONFIG_BOOTCOMMAND "dhcp; bootm" +#define CONFIG_BOOTCOMMAND "nand read 30008000 0x80000 300000;bootm" #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ @@ -127,7 +144,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "[ ~nicholas@anycle.com ]# " /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -136,7 +153,7 @@ #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x30008000 /* default load address */ /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ /* it to wrap 100 times (total 1562500) to get 1 sec. */ @@ -173,6 +190,7 @@ /* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */ #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ +//#define CONFIG_SST_VF1601 1 /* uncomment this if you have a AM29LV160DB flash */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -192,15 +210,54 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ #define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +//#define CONFIG_ENV_IS_IN_FLASH 1 +//#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C + +#define CONFIG_DRIVER_S3C24X0_I2C 1 +#define CONFIG_HARD_I2C 1 + +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7f + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 + +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0X60000 +#define CONFIG_ENV_SIZE 0x20000 + +#ifdef CONFIG_SST_VF1601 +#define PHYS_FLASH_SIZE 0x00200000 +#define CONFIG_SYS_MAX_FLASH_SECT (32) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#endif + /*----------------------------------------------------------------------- * NAND flash settings */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_S3C2440 +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_NAND_BASE 0x4E000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define SECTORSIZE_2K 2048 +#define NAND_SECTOR_SIZE SECTORSIZE +#define NAND_SECTOR_SIZE_2K SECTORSIZE_2K +#define NAND_BLOCK_MASK 511 +#define NAND_BLOCK_MASK_2K 2047 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_SYS_64BIT_VSPRINTF #endif /* CONFIG_CMD_NAND */ #define CONFIG_SETUP_MEMORY_TAGS @@ -212,10 +269,65 @@ #define CONFIG_CMDLINE_EDITING -#ifdef CONFIG_CMDLINE_EDITING -#undef CONFIG_AUTO_COMPLETE -#else +//#ifdef CONFIG_CMDLINE_EDITING +//#undef CONFIG_AUTO_COMPLETE +//#else #define CONFIG_AUTO_COMPLETE +//#endif + +#if 1 +//#define CONFIG_USB_OHCI +//#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_DEVICE_DEREGISTER +#define CONFIG_SUPPORT_VFAT +#define LITTLEENDIAN +#endif + +#define CONFIG_JFFS2_NAND 1 +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0X480000 +#define CONFIG_JFFS2_PART_OFFSET 0x80000 + +#define CONFIG_JFFS2_CMDLINE 1 +#define MTDIDS_DEFAULT "nand0=nandflash0" +#define MTDPARTS_DEFAULT "mtdparts=nandflash0:384k(bootloader),"\ + "128k(params),"\ + "5m(kernel),"\ + "-(root)" + +#define ENABLE_CMD_LOADB_X 1 +#define ENABLE_CMD_NAND_YAFFS 1 +#define ENABLE_CMD_NAND_YAFFS_SKIPFB 1 + +#if 0 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO +#define CONFIG_VIDEO_S3C2410 +#define CONFIG_VIDEO_LOGO +#define CONFIG_FB_16BPP_PIXEL_SWAP + +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (240*320 + 1024 + 100) +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_CMD_UNZIP +#define LCD_VIDEO_ADDR 0x33d00000 + +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +#endif + +#if 0 +#define CONFIG_CMD_MMC +#define CONFIG_MMC 1 +#define CONFIG_MMC_S3C 1 +#define CFG_MMC_BASE 0xff000000 #endif #endif /* __CONFIG_H */
4.Others config file:
diff -uNr u-boot-2009.08_0319_ok/common/serial.c u-boot-2009.08_nand/common/serial.c
--- u-boot-2009.08_0319_ok/common/serial.c 2017-03-19 15:24:58.000000000 +0800
+++ u-boot-2009.08_nand/common/serial.c 2017-04-25 09:46:58.722041514 +0800
@@ -59,7 +59,7 @@
#else
return &serial0_device;
#endif
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
#if defined(CONFIG_SERIAL1)
return &s3c24xx_serial0_device;
#elif defined(CONFIG_SERIAL2)
@@ -134,7 +134,7 @@
#if defined (CONFIG_STUART)
serial_register(&serial_stuart_device);
#endif
-#if defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
serial_register(&s3c24xx_serial0_device);
serial_register(&s3c24xx_serial1_device);
serial_register(&s3c24xx_serial2_device);
diff -uNr u-boot-2009.08_0319_ok/cpu/arm920t/s3c24x0/usb.c u-boot-2009.08_nand/cpu/arm920t/s3c24x0/usb.c
--- u-boot-2009.08_0319_ok/cpu/arm920t/s3c24x0/usb.c 2017-03-19 15:24:55.000000000 +0800
+++ u-boot-2009.08_nand/cpu/arm920t/s3c24x0/usb.c 2017-04-24 15:26:52.567985959 +0800
@@ -24,11 +24,11 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
#if defined(CONFIG_S3C2400)
# include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
# include <s3c2410.h>
#endif
@@ -68,5 +68,5 @@
return 0;
}
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
+# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) defined(CONFIG_S3C2440) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff -uNr u-boot-2009.08_0319_ok/cpu/arm920t/s3c24x0/usb_ohci.c u-boot-2009.08_nand/cpu/arm920t/s3c24x0/usb_ohci.c
--- u-boot-2009.08_0319_ok/cpu/arm920t/s3c24x0/usb_ohci.c 2017-03-19 15:24:55.000000000 +0800
+++ u-boot-2009.08_nand/cpu/arm920t/s3c24x0/usb_ohci.c 2017-04-25 09:57:27.334036751 +0800
@@ -40,7 +40,7 @@
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
#include <s3c2410.h>
#endif
diff -uNr u-boot-2009.08_0319_ok/drivers/i2c/s3c24x0_i2c.c u-boot-2009.08_nand/drivers/i2c/s3c24x0_i2c.c
--- u-boot-2009.08_0319_ok/drivers/i2c/s3c24x0_i2c.c 2017-03-19 15:24:55.000000000 +0800
+++ u-boot-2009.08_nand/drivers/i2c/s3c24x0_i2c.c 2017-04-24 15:29:54.219978865 +0800
@@ -29,7 +29,7 @@
#include <common.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
#include <s3c2410.h>
#endif
#include <i2c.h>
@@ -60,7 +60,7 @@
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
return (gpio->GPEDAT & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
@@ -79,7 +79,7 @@
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
-#ifdef CONFIG_S3C2410
+#if defined( CONFIG_S3C2410 ) || defined(CONFIG_S3C2440)
gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
#endif
#ifdef CONFIG_S3C2400
@@ -136,7 +136,7 @@
}
if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
-#ifdef CONFIG_S3C2410
+#if defined( CONFIG_S3C2410 ) || defined(CONFIG_S3C2440)
ulong old_gpecon = gpio->GPECON;
#endif
#ifdef CONFIG_S3C2400
@@ -144,7 +144,7 @@
#endif
/* bus still busy probably by (most) previously interrupted transfer */
-#ifdef CONFIG_S3C2410
+#if defined( CONFIG_S3C2410 ) || defined(CONFIG_S3C2440)
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
#endif
@@ -168,7 +168,7 @@
udelay (1000);
/* restore pin functions */
-#ifdef CONFIG_S3C2410
+#if defined( CONFIG_S3C2410 ) || defined(CONFIG_S3C2440)
gpio->GPECON = old_gpecon;
#endif
#ifdef CONFIG_S3C2400
diff -uNr u-boot-2009.08_0319_ok/drivers/usb/host/ohci-hcd.c u-boot-2009.08_nand/drivers/usb/host/ohci-hcd.c
--- u-boot-2009.08_0319_ok/drivers/usb/host/ohci-hcd.c 2017-03-19 15:24:55.000000000 +0800
+++ u-boot-2009.08_nand/drivers/usb/host/ohci-hcd.c 2017-04-24 15:31:41.611974672 +0800
@@ -67,6 +67,7 @@
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410) || \
+ defined(CONFIG_S3C2440) || \
defined(CONFIG_S3C6400) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
diff -uNr u-boot-2009.08_0319_ok/include/common.h u-boot-2009.08_nand/include/common.h
--- u-boot-2009.08_0319_ok/include/common.h 2017-03-19 15:24:56.000000000 +0800
+++ u-boot-2009.08_nand/include/common.h 2017-04-24 15:33:14.735971035 +0800
@@ -493,7 +493,7 @@
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)
ulong get_FCLK (void);
ulong get_HCLK (void);
diff -uNr u-boot-2009.08_0319_ok/include/serial.h u-boot-2009.08_nand/include/serial.h
--- u-boot-2009.08_0319_ok/include/serial.h 2017-03-19 15:24:56.000000000 +0800
+++ u-boot-2009.08_nand/include/serial.h 2017-04-24 15:33:59.263969296 +0800
@@ -37,7 +37,7 @@
#endif
-#if defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
extern struct serial_device s3c24xx_serial0_device;
extern struct serial_device s3c24xx_serial1_device;
extern struct serial_device s3c24xx_serial2_device;
diff -uNr u-boot-2009.08_0319_ok/lib_arm/board.c u-boot-2009.08_nand/lib_arm/board.c
--- u-boot-2009.08_0319_ok/lib_arm/board.c 2017-03-19 15:24:58.000000000 +0800
+++ u-boot-2009.08_nand/lib_arm/board.c 2017-04-24 16:54:17.135781156 +0800
@@ -172,7 +172,7 @@
printf ("\n\n%s\n\n", version_string);
#if defined(CONFIG_MINI2440_LED)
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();//s3c24x0_get_base_gpio();
gpio->GPBDAT = 0x101;
#endif
printf("\n\n%s\n\n", version_string);
@@ -317,7 +317,7 @@
#endif
#if defined(CONFIG_MINI2440_LED)
- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();//s3c24x0_get_base_gpio();
#endif
/* Pointer is writable since we allocated a register for it */
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